P4 Workshop 2016

The Paxos protocol is the foundation for building many fault-tolerant distributed systems and services. This talk posits that there are significant performance benefits to be gained by implementing Paxos logic in network devices. Until recently, the notion of a switch-based implementation of Paxos would be a daydream. However, new flexible hardware and expressive data plane programming languages are on the horizon and will provide customizable packet processing pipelines needed to implement Paxos. This talk describes an implementation of Paxos in one of those languages, P4, as well as our on-going efforts to evaluate the implementation on a variety of hardware devices. Implementing Paxos provides a critical use case for P4, and will help drive the requirements for data plane languages in general. In the long term, we imagine that consensus could someday be offered as a network service, just as point-to-point communication is provided today.

Virtualized data-centers use software hypervisor switches to steer packets to and from virtual machines (VMs). The switch frequently needs upgrading and customization---to support new protocol headers or encapsulations for tunneling or overlays, to improve measurement and debugging features, and even to add middlebox-like functions. Software switches are typically based on a large body of code, including kernel code. Changing the switch is a formidable undertaking requiring domain mastery of network protocol design and developing, testing, and maintaining a large, complex code-base. In this talk, we argue that changing how a software switch forwards packets should not require intimate knowledge of its implementation. Instead, it should be possible to specify how packets are processed and forwarded in a high-level domain-specific language (DSL) such as P4, then compiled down to run on the underlying software switch. We present PISCES, a software switch that is not hard-wired to specific protocols, which eases adding new features. We also show how the compiler can analyze the high-level specification to optimize forwarding performance. Our evaluation shows that PISCES performs comparably to Open vSwitch, a hardwired hypervisor switch, and that PISCES programs are about 40 times shorter than equivalent Open vSwitch programs. 

*This presentation also has an associated demo: PISCES: A Programmable, Protocol-Independent Software Switch* 

In cooperation with Ericsson our team from Eötvös Loránd University, Budapest, Hungary works on a P4 compiler that separates the hardware specific and hardware independent program functionalities. According to this design, the core compiler generates a target independent core program that relies on a target-specific hardware abstraction library representing an abstraction layer between the actual hardware and the P4 program. This design enables us to switch to a new hardware without writing a new P4 compiler and recompiling the original P4 program, since the core program always remains the same and the underlying target-specific library will only be changed. In this talk, we will present the current status of our target independent core compiler, the challenges we faced during the development, an Intel DPDK-based implementation of the hardware abstraction library and the performance test results. According to the first experiments, our DPDK-based L2 switch compiled from a P4 code can reach 9.1 Gbps forwarding rate on a single core setup with 10 Gbps line cards and Ethernet probe packets of 64 bytes. The testbed preparation for 40 Gbps and other more complex scenarios is on going. 

Switches today provide a small set of scheduling algorithms. While we can tweak scheduling parameters, we cannot modify algorithmic logic, or add a completely new algorithm, after the switch has been designed. This paper presents a design for a programmable packet scheduler, which allows scheduling algorithms—potentially algorithms that are unknown today—to be programmed into a switch without requiring hardware redesign.

Our design builds on the observation that scheduling algorithms make two decisions: in what order to schedule packets and when to schedule them. Further, in many scheduling algorithms these decisions can be made when packets are enqueued. We leverage this observation to build a programmable scheduler using a single abstraction: the push-in first-out queue (PIFO), a priority queue that maintains the scheduling order and time for such algorithms.

We show that a programmable scheduler using PIFOs lets us program a wide variety of scheduling algorithms. We present a detailed hardware design for this scheduler for a 64-port 10 Gbit/s shared-memory switch with <4% chip area overhead on a 16-nm standard-cell library. Our design lets us program many sophisticated algorithms, such as a 5-level hierarchical scheduler with programmable scheduling algorithms at each level.

Closing Remarks